High Channel Count Neural Signal Processing

Description: This research project aims to develop a power-area efficient NSP capable of preserving useful neural data information while achieving a high compression rate. We have analyzed and applied techniques from signal detection theory and pattern recognition to neural signals, resulting in reliable spike-sorting algorithms which are robust to neural noise. Streaming digital hardware architectures have been developed with the goal of implementing these algorithms on-chip, enabling significant power and area savings without loss of sorting performance compared to existing NSPs. Statistical analysis on neural signals is now being performed to optimize design parameters and minimize hardware cost. Future research will focus on integrating a complete spike-sorting processing chain into a fully implantable VLSI architecture capable of processing a massive data from thousands of simultaneously recorded neurons.