|Maximum Load||1 kVA|
|Power Density||> 25 W/in3|
|Volume||< 40 in3|
|Voltage Input||200 VDC|
|Voltage Output||120 VAC RMS|
|Frequency Output||60 Hz|
|Maximum Outer Temperature||< 60 ºC|
|Electromagnetic Compliance||FCC Part 15 B|
The group will model four initial designs using PSpice. The group will buy a commercial inverter (designed for 12 VDC use), reverse engineer the layout, and model; close attention paid to board layout.
The group will analyze the PSpice models from phase one and select the best with regards to efficiency and practicability. This design will be prototyped and the current will be increased to find the power limits of the material being worked with beginning with silicon transistors.
The proposed design from phase one is prototyped using updated materials (gallium nitride and/or silicon carbide). Power is stepped up to test new materials for their limit.
The chosen design is built with the use of printed circuit boards, custom enclosure, and heat solutions. Extensive testing is performed at objective specifications while design issues are troubleshooted and solved.
This is an overhead view of the prototyped circuit for the gate drivers and H-bridge configuration using four IRF530 N-Channel MOSFETs.
The above schematic is the teams proposed design solution for the inverter. This schematic was used as a basic building block for creating the final inverter circuit.
After finishing the H-bridge design the group designed an LC resonant filter to obtain the pulse width modulated sine wave of 60 Hz.
After prototyping the H-bridge architecture a high voltage supply was connecting to the DC rail of the the prototype. This picture shows the inverted PWM at the output of the bridge.
As pictured above from left to right: Philip Beard, Jacob Brettrager, Jack Grundemann, Stanley Karas, and Travis Meade.