Compact DC/AC Power Inverter
200 VDC to 120 VAC Conversion

Team seven will design their own power inverter inspired by the Little Box Challenge, a contest hosted by Google and IEEE. The Little Box Challenge is to create an inverter both very small, 40 cubic inches, and also powerful enough to rival the output of its larger counterparts. Accomplishing this small form factor would be an important step in attaining widespread high power inverter utilization. This would also increase the feasibility of solar power generation for the masses in the future.

Project Specifications

Maximum Load 1 kVA
Power Density > 25 W/in3
Volume < 40 in3
Voltage Input 200 VDC
Voltage Output 120 VAC RMS
Frequency Output 60 Hz
Maximum Outer Temperature < 60 ºC
Electromagnetic Compliance FCC Part 15 B

Design Phase 1

The group will model four initial designs using PSpice. The group will buy a commercial inverter (designed for 12 VDC use), reverse engineer the layout, and model; close attention paid to board layout.

Design Phase 2

The group will analyze the PSpice models from phase one and select the best with regards to efficiency and practicability. This design will be prototyped and the current will be increased to find the power limits of the material being worked with beginning with silicon transistors.

Design Phase 3

The proposed design from phase one is prototyped using updated materials (gallium nitride and/or silicon carbide). Power is stepped up to test new materials for their limit.

Design Phase 4

The chosen design is built with the use of printed circuit boards, custom enclosure, and heat solutions. Extensive testing is performed at objective specifications while design issues are troubleshooted and solved.

Project Snapshots

Overhead Board Layout

This is an overhead view of the prototyped circuit for the gate drivers and H-bridge configuration using four IRF530 N-Channel MOSFETs.

Side View Board Layout

This is a side view of the prototyped circuit for the gate drivers and H-bridge configuration using four IRF530 N-Channel MOSFETs

Proposed Inverter Schematic

The above schematic is the teams proposed design solution for the inverter. This schematic was used as a basic building block for creating the final inverter circuit.

PSpice Simulation

After deciding on a basic H-bridge design for the inverter initial testing was done in PSPice to see how pulse width modulation (PWM) would work in driving the gates of the four MOSFETs.

Filtered Sine Wave and PWM

After finishing the H-bridge design the group designed an LC resonant filter to obtain the pulse width modulated sine wave of 60 Hz.

Silicon Testing Process

Once a prototyped silicon circuit had been completed on a proto board the group setup a test circuit to run 30 VDC at 430 mA through a 40 Ω load rated at 40 W. This allowed the group to collect relevant data to power absorption of the MOSFETs.

Lab Testing Pulse Width Modulation

After prototyping the H-bridge architecture a high voltage supply was connecting to the DC rail of the the prototype. This picture shows the inverted PWM at the output of the bridge.

Lab Testing LC Filter

Once the LC filter was designed the group tested the final result and displayed the output of the H-bridge across the load on the oscilloscope. The figure above shows the final signal being outputs by the H-bridge inverter.

The Team

Team 7

As pictured above from left to right: Philip Beard, Jacob Brettrager, Jack Grundemann, Stanley Karas, and Travis Meade.

Team 7 ECE 480