James Lee

Rahul Dey

Computer Vision | Machine Learning | PhD Student

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About Me

Hi! I am a fifth year Graduate Student in the Computer Science and Engineering Department at Michigan State University pursuing my PhD degree under the supervision of Dr. Vishnu Boddeti. I received my bachelor's and master's (dual) degrees from the Electronics and Electrical Communication Engineering Department at the Indian Institute of Technology, Kharagpur in 2013.

I work in the Human Analysis Lab (HAL) at MSU as a research assistant. My research interests lie in the intersection of Generative and Facial 3D models. Specifically, I focus on the problem of recovering occluded regions in face images, both in 2D (aka Face Completion) and 3D. I have worked on 3D-aware inpainting of masked face images (3DFaceFill) where we leverage explicit 3D priors and facial symmetry for face completion. In 3D, I have worked on generating occlusion-robust and diverse 3D reconstructions corresponding to a single occluded face image (Diverse3DFace). My previous paper, RankGAN: A Maximum Margin Ranking GAN for Generating Faces won the Best Student Paper Award at the ACCV 2018. I had earlier also been associated with the Connected and Autonomous Vehicles (CANVAS) project at MSU directed, where I worked on the pose estimation of cars in the presence of occlusion.

Latest Projects

Academic Projects

Research Assistant - Michigan State University, USA (2016 - Present)

  • Evolved a new margin-based ranking loss function and training framework to train GANs progressively without changing the network architecture. Best student paper award at ACCV'18.
  • Currently working on a project to perform successful alignment on vehicles, faces, etc. using a modular framework that is supposed to outperform single network models in the present of occlusion.

Master of Technology Thesis Project - IIT Kharagpur, India (2013)

  • Engineered an efficient FPGA based architecture of Motion Estimation block for H.264 video codec using the novel and fast Adaptive Rood Pattern Search algorithm which improved computation time by up to 50%
  • Achieved clock rate of 110 MHz on a Virtex 5 FPGA board with a low device utilization of 3k gate equivalent.

Bachelor of Technology Thesis Project - IIT Kharagpur, India (2012)

  • Designed a robust OCR system for printed text that recognizes multiple fonts in various scripts with high accuracy of ~90% over 100 different fonts and ~99% for most commonly used fonts in English.

Work Experience

Research & Development Engineer - Logic Fruit Technologies, Gurgaon (India) (2015 - 2016)

  • Engineered an INR 10 million project for DRDO, India to develop a mobile border surveillance embedded system that detects motion changes in real time with object tracking using rotating CCD/Thermal cameras.
  • Brainstormed the entire algorithm including pre-processing, frame-registration, change detection, tracking and archival and its optimized FPGA architecture to use minimal resources and make it work in all kinds of weather and background conditions including haze, high noise, low contrast and thermal vision.

Software Engineer - Electronic Arts Games, Hyderabad (India) (2013 - 2015)

  • Developed automation and web tools for load testing, system capacity analysis and forecasting of game servers that reduced manual work of 2-3 days to a few hours, reduced system downtime risks and improved preparedness.
  • Credited in the game credits of the title Need for Speed 2016 for my contribution in the system testing and analysis of NFS servers that led to its smooth and flawless release.