;Displays value in $2000 on LCD in binary format
DISPLAY	LDX	#$FFFF
	LDAA 	#$00
	STAA	$0240	; configure RW, RS and EN on LCD as low
	JSR	DELAY
	LDAA	#$0F
	STAA	$0242	; turn Port T outputs on for controlling the LCS
	JSR 	DELAY
	LDAA	#$FE
	STAA	$0252	; sets bit 3 as output
	JSR	DELAY
	LDAA	#$08
	STAA	$0250	; sets bit 3 high and enables U7
	JSR	DELAY
	LDAA	#$82
	STAA	$024A	; sets bit 7 as output for controlling U21
	JSR	DELAY
	LDAA	#$80
	STAA	$0248	; U21_EN is set high enabling U21
	JSR	DELAY
	LDAA	#$0F
	STAA	$025A	; sets bit 0, 1, 2 and 3 as outputs for LCD-DB4, 5, 6, and 7
	JSR	DELAY
	LDAA	#$00
	STAA	$0258	; sets LCD data bits as low
	JSR	DELAY
	LDAA	#$03
	STAA	$0258
	JSR 	DELAY
	LDAA	#$08
	STAA	$0240
	JSR	DELAY
	LDAA	#$00
	STAA	$0240
	JSR	DELAY
	LDAA	#$03
	STAA	$0258
	JSR	DELAY
	LDAA	#$08
	STAA	$0240
	JSR	DELAY
	LDAA	#$00
	STAA	$0240
	JSR	DELAY
	LDAA	#$03
	STAA	$0258
	JSR	DELAY
	LDAA	#$08
	STAA	$0240
	JSR	DELAY
	LDAA	#$00
	STAA	$0240
	JSR	DELAY
	LDAA	#$02
	STAA	$0258
	JSR	DELAY
	LDAA	#$08
	STAA	$0240
	JSR	DELAY
	LDAA	#$00
	STAA	$0240	; puts the LCD in four-bit mode
	JSR	DELAY
	LDAA	#$02
	STAA	$0258
	JSR	DELAY
	LDAA	#$08
	STAA	$0240
	JSR	DELAY
	LDAA	#$00
	STAA	$0240
	JSR	DELAY
	LDAA	#$0C
	STAA	$0258
	JSR	DELAY
	LDAA	#$08
	STAA	$0240
	JSR	DELAY
	LDAA	#$00
	STAA	$0240	; sends the command $2C
	JSR	DELAY
	LDAA	#$00
	STAA	$0258
	JSR	DELAY
	LDAA	#$08
	STAA	$0240
	JSR	DELAY
	LDAA	#$00
	STAA	$0240
	JSR	DELAY
	LDAA	#$06
	STAA	$0258
	JSR	DELAY
	LDAA	#$08
	STAA	$0240
	JSR	DELAY
	LDAA	#$00
	STAA	$0240	; sends the command $06
	JSR	DELAY
	LDAA	#$00
	STAA	$0258
	JSR	DELAY
	LDAA	#$08
	STAA	$0240
	JSR	DELAY
	LDAA	#$00
	STAA	$0240
	JSR	DELAY
	LDAA	#$0F
	STAA	$0258
	JSR	DELAY
	LDAA	#$08
	STAA	$0240
	JSR	DELAY
	LDAA	#$00
	STAA	$0240	; sends the command $0F
	JSR	DELAY
	LDAA	#$00
	STAA	$0258
	JSR	DELAY
	LDAA	#$08
	STAA	$0240
	JSR	DELAY
	LDAA	#$00
	STAA	$0240
	JSR	DELAY
	LDAA	#$01
	STAA	$0258
	JSR	DELAY
	LDAA	#$08
	STAA	$0240
	JSR	DELAY
	LDAA	#$00
	STAA	$0240	; sends the command $01
	JSR	DELAY
	LDAA 	#$04
	STAA 	$0240	; selects the data register for writing
	JSR	DELAY

	LDAA	$2000
	LSRA
	LSRA
	LSRA
	LSRA
	LSRA
	LSRA
	LSRA		; shift right 7 times
	STAA	$2001
	BCLR	$2001,%11111110
	JSR	DATA

	LDAA	$2000
	LSRA
	LSRA
	LSRA
	LSRA
	LSRA
	LSRA		; shift right 6 times
	STAA	$2001
	BCLR	$2001,%11111110
	JSR	DATA

	LDAA	$2000
	LSRA
	LSRA
	LSRA
	LSRA
	LSRA		; shift right 5 times
	STAA	$2001
	BCLR	$2001,%11111110
	JSR	DATA

	LDAA	$2000
	LSRA
	LSRA
	LSRA
	LSRA		; shift right 4 times
	STAA	$2001
	BCLR	$2001,%11111110
	JSR	DATA

	LDAA	$2000
	LSRA
	LSRA
	LSRA		; shift right 3 times
	STAA	$2001
	BCLR	$2001,%11111110
	JSR	DATA

	LDAA	$2000
	LSRA
	LSRA		; shift right 2 times
	STAA	$2001
	BCLR	$2001,%11111110
	JSR	DATA

	LDAA	$2000
	LSRA		; shift right 1 time
	STAA	$2001
	BCLR	$2001,%11111110
	JSR	DATA

	LDAA	$2000
	STAA	$2001	; shift right 0 times
	BCLR	$2001,%11111110
	JSR	DATA

	RTS

DELAY	DEX
	BNE	DELAY
	LDX	#$FFFF
	RTS

DATA	LDAB	#$03	; convert to ascii +$30
	STAB	$0258
	JSR 	DELAY
	LDAB	#$0C
	STAB	$0240
	JSR	DELAY
	LDAB	#$00
	STAB	$0240
	JSR 	DELAY
	LDAB	$2001
	STAB	$0258
	JSR 	DELAY
	LDAB	#$0C
	STAB	$0240
	JSR	DELAY
	LDAB	#$00
	STAB	$0240
	RTS