COURSE OUTLINE -- Spring 2003

ECE 410 -- VLSI Design, 4 Credits

Instructor Dr. Chin-Long Wey, wey@egr.msu.edu
2211 Engineering Building (EB)
Phone: 517-353-0665; Fax: 517-353-1980
Time & Place  Lecture: 11:30am - 12:20pm, 1145 EB.
Lab: 3230 EB
Office Hours 10:00-11:00am (W,F), 1:30-2:30pm (M), and other time by appointment 
Textbook  Introduction to VLSI Design, by J.P. Uyemura, Wiley, 2002
References  K. Martin, Digital Integrated Circuit Design, 2000.
Weste and Eshraghian, Principles of CMOS VLSI Design, 2nd Ed., 1993.
Digital Integrated Circuits by J.M. Rabaey, Prentice Hall, 1995
Design of VLSI Systems, by D. Mlynek and Y. Leblebici, Webcourse.
Supplementary class notes and pertinent technical papers will be provided when appropriate. 

Grading System
 
Lab
Exams 
Homeworks & Quizzes
TOTAL		 150 points 
300 points 
  50 points
500 points		 425 - 500 
375 - 425 
350 - 375 
325 - 350 		 4.0 
3.5 
3.0 
2.5 		 300 - 325 
275 - 300 
250 - 275 
below 250 		 2.0 
1.5 
1.0 
0.0 

Rules for Lecture

    1. Final grade will be 0.0 if the lab grade is less than 75 points.
    2. There are NO MAKE UP EXAMS. One exam from Exams #1-#3 will be dropped in computing your grade.

      3. IMPOTANT DATES --
      •  Exam # 1 -- 1/24 (Friday)
      •  Exam # 2 -- 2/19 (Wednesday)
      •  Exam # 3 -- 3/19 (Wednesday)
      •  Exam # 4 -- 4/16 (Wednesday) (Comprehensive Exam)
    3. Quizzes will be open books and notes. There are NO MAKE UP QUIZZES.
    4. Late homework WILL NOT be accepted.
    5. Attendance --
      • Perfect attendance   -- 20 points bonus
      • # of absences <= 2  -- 10 points bonus
      • # of absences <= 5  -- Final grade MAY BE curved
      • # of absences  >  5  -- Final grade WILL NOT BE curved
      • # of absences  >10  -- Final grade WILL BE 0.0 IF TOTAL POINT IS LESS THAN 375.

Course Outline
Topics
 Reading
Lecture Unit #1:  Overview and Background
                   a.  VLSI Design
                   b.  Logic Design with CMOS 
                   c.  Properties of Digital Circuits
Chapter 1
Chapter 2
Lecture Unit #2:  CMOS Devices and Integrated Circuits
                   a.  CMOS Devices
                   b.  Electrical Characteristics of MOSFETs
                   c.  Electronic Analysis of CMOS Gates
Chapters 3,4,5
Chapter 6
Chapter 7
Lecture Unit #3:  CMOS Combinational Logic Circuits
                   a.  VLSI System - Combinational Components
                   b.  Arithemtic Circuits in CMOS VLSI
Chapter 11
Chapter 12
Lecture Unit #4:  CMOS Sequential Logic Circuits
                   a.  VLSI System - Sequential Components
                   b.  Memories and Programmable Logic
Chapter 11
Chapter 13
Lecture Unit #5:  Advanced Topics
                   a.  Design Issues - Design Techniques, High-Speed, Low-Power
                   b.  Mixed-Signal ICs
                   c.  System-Level Integration Issues
                   d.  Quality Issues - Testability, Reliability, Manufacturability
Chapters 8,9,15
Handouts
Chapter 14
Chapter 16

Tentative Schedule
1/6 - 1/22  Lecture Unit #1 -- Overview and Background   (****1/20 -- No class ****)
1/24 Exam #1 (Friday)
1/27-2/17 Lecture Unit #2 -- CMOS Devices and Integrated Circuits
2/19 Exam #2 (Wednesday)
2/21-3/17 Lecture Unit #3 -- CMOS Combinational Logic Circuits
3/19-3/24 Lecture Unit #4(a) -- CMOS Sequential Logic Circuits
3/26 Exam #3 (Wednesday)
3/21-4/9 Lecture Unit #4(b) -- CMOS Sequential Logic Circuits
4/11-4/14 Lecture Unit #5(a)(c) -- Design Issues
4/16 Exam #4 (Wednesday)
4/18-4/25 Lecture Unit #5 -- Advanced Topics
 
Homework Assignment