Dr. Chin-Long Wey, Professor
Department of Electrical and Computer Engineering
Michigan State University
East Lansing, MI 48824-1226
Phone: 517-353-0665; Fax: 517-353-1980
E-mail: wey@egr.msu.edu

Complete Publication List 

Journal Papers
Book Chapters
Conference Papers
Short Courses/Tutorials

A. Journal Papers

  1. C.-c. Wu, K. Nakajima, C.L. Wey, and R. Saeks, "Analog Fault Diagnosis with Failure Bounds," IEEE Trans. on Circuits and Systems, Vol. CAS-29, No.5, pp.277-284, May 1982.
  2. C.L. Wey and R. Saeks, "On the Implementation of Analog ATPG: The Linear Case,"IEEE Trans. on Instrumentation and Measurement, Vol. IM-34, No.3, pp.442-449, September 1985.
  3. C.L. Wey, "A Decision Process for Analog System Fault DiagnosisIEEE Trans. on Circuits and Systems, Vol. CAS-34, No.1, pp.107-109, January 1987.
  4. C.L. Wey, M.K. Vai, and F. Lombardi, "On the Design of a Redundant PLA," IEEE Journal of Solid-State Circuits. Vol. SC-22, No.1, pp.114-117, February 1987.
  5. C.L. Wey and F. Lombardi, "On the Repair of Redundant RAM's," IEEE Trans. on CAD of Integrated Circuits and Systems. Vol. CAD-6, No.2, pp.222-231. March, 1987.
  6. CL. Wey and F. Lombardi, "On the Novel Self-test Approach to Digital Test," The Journal of Computers, Vol.30, No.3, pp.258-267, March 1987.
  7. C.L. Wey, "Design of Testability for Analog Fault Diagnosis," International Journal of Circuit Theory and Application, Vol.15, No.2, pp.123-142, April 1987.
  8. F. Lombardi and C.L. Wey, "Algorithms for Functional Testing of Digital Systems," (Invited Paper) International Journal of Electronics, Vol.62, No.5, pp.707-732, May 1987.
  9. B.L. Jiang, C.L. Wey, and L.J Fan, "Fault Prediction for Analog Circuits," Journal of Circuits, Systems, and Signal Process. Vol.7, No.1, pp.95-109, January 1988.
  10. Chan, S.-W. and C.L. Wey, "The Design of Concurrent Error Diagnosable Systolic Arrays for Band-Matrix Multiplication," IEEE Trans. on CAD of Integrated Circuits and Systems (Special issue on Testable and Maintainable Design), Vol. CAD-7, No.1, pp.21-37, January 1988.
  11. S.-W. Chan, S.S. Leung, and C.L. Wey, "A Systematic Design Strategy for Concurrent Error Diagnosable Iterative Logic Arrays," IEE Proceedings, Part E, Computers and Digital Techniques, Vol.135, No.2, pp.87-94, March 1988.
  12. C.L. Wey, "On Yield Considerations for the Design of Redundant Programmable Logic Arrays," IEEE Trans. on CAD of Integrated Circuits and Systems, Vol. CAD-7, No.4, pp.528-535, April 1988.
  13. C.L. Wey and R. Saeks, "On the Implementation of Analog ATPG: The Nonlinear Case," IEEE Trans. on Instrumentation and Measurement, Vol. IM-37, No.2, pp.252-258. June 1988.
  14. C.L. Wey, "Parallel Processing for Analog Fault Diagnosis," International Journal of Circuit Theory and Application, Vol.16, pp.303-316, July 1988.
  15. B.L. Jiang and C.L. Wey, "Fault Prediction Process for Large Analog Circuit Networks," International Journal of Circuit Theory and Application. Vol.17, No.2, pp.141-149, April 1989.
  16. C.L. Wey and S.M. Chang, "Test Generation for C-testable Array Dividers," IEE Proceedings, Part E, Computers and Digital Techniques, Vol.136, No.5, pp.434-442, September 1989.
  17. T.Y. Chang and C.L. Wey, "Design of fault diagnosable and repairable PLA," IEEE Journal of Solid-State Circuits. Vol. SC-24, No.5, pp.1451-1454, October 1989.
  18. C.L. Wey and T.Y. Chang, "An Efficient Output Phase Assignment for PLA Minimization," IEEE Trans. on CAD of Integrated Circuits and Systems, Vol.9, No.1, pp.1-7, January 1990.
  19. C.L. Wey, "Built-In Self-Test (BIST) Structure for Analog Circuits Fault Diagnosis," IEEE Trans. on Instrumentation and Measurement. Vol. IM-39, No.2, pp.517-521, June 1990.
  20. C.L. Wey and T.Y. Chang, "Design of VLSI-Based Parallel Multipliers," IEE Proceedings, Part E, Computers and Digital Techniques. Vol.137, No.4, pp.328-336, July1990.
  21. B.L. Jiang and C.L. Wey, "Fault Prediction for Analog Circuits - Reply," Journal of Circuits, Systems, and Signal Process. Vol.9, No.4, pp.503-503, July 1990.
  22. C.L. Wey, T.Y. Chang, and J.Y. Ding, "Design of Fault Diagnosable and Repairable Folded PLAs for Yield Enhancement," IEEE Journal of Solid-State Circuits. Vol.26, No.1,pp.54-57, January 1991.
  23. C.L. Wey, "Alternative Built-In Self-Test Structure (BIST) for Analog Circuit Fault Diagnosis," Electronics Letters. Vol.27, No.18, pp.1627-1628, August 1991.
  24. C.L. Wey, "Concurrent Error Detection in Current-Mode A/D Converter," Electronics Letters. Vol.27, No.25, pp.2370-2372, December 1991.
  25. C.L. Wey, "Concurrent Error Detection in Array Dividers by Alternating Input Data," IEE Proceedings, Part E, Computers and Digital Techniques. Vol.139, No.2, pp.123-130, March 1992.
  26. C.L. Wey and S. Krishnan, "An Accurate Current-mode Divide-by-two Circuit," Electronics Letters. Vol.28, No.9, pp.820-822, April 1992.
  27. C.L. Wey and S. Krishnan, "Built-In Self-Test (BIST) Structures for Analog Circuit Fault Diagnosis with Current Test Data," IEEE Trans. on Instrumentation and Measurement, Vol. IM-41, No.4, pp.535-539, August 1992.
  28. C.L. Wey, S. Krishnan, and S. Sahli, "Design of Concurrent Error Detectable Current-Mode A/D converters for Real-time Applications," Analog Integrated Circuits and Signal Processing, No.4, pp.65-74, July 1993.
  29. S. Krishnan and C.L. Wey, "An Accurate Reference-generating Circuit for Successive Approximation Current-mode A/D Converters," International Journal of Circuit Theory and Application. No.21, pp.361-369, August 1993.
  30. M.-D. Shieh, C.L. Wey, and P.D. Fisher, "Fault Effects in Asynchronous Sequential Logic Circuits," IEE Proceedings, Part E, Computers and Digital Techniques. Vol. 140, No.6, pp.327-332, November 1993.
  31. J.-W. Kang, P.D. Fisher, and C.L. Wey, "An Efficient Modeling and Synthesis Procedure of Asynchronous Sequential Logic Circuits," IEE Proceedings, Part E, Computers and Digital Techniques. Vol.141, No.1, pp. 61-64, January 1994.
  32. C.L. Wey, N. Berthlot, and B. Veltkamp, "Concurrent Error Detection in High Speed Carry-free Dividers," IEE Proceedings, Computers and Digital Techniques, Vol.141, No.6, pp.356-360, November 1994
  33. C.S. Lai and C.L. Wey, "SOLiT: An Automated system for Synthesizing Reliable Sequential Circuits with Multi-level Logic Implementation," IEE Proceedings, Computers and Digital Techniques, Vol.142, No.1, pp.49-54, January 1995.
  34. R. Huang and C.L. Wey, "Simple Yet Accurate Current Copiers for Low-Voltage Current-Mode Signal Processing Applications," International Journal of Circuit Theory and Application, vol.23, pp.137-145, No.2, March 1995.
  35. C.L. Wey, "Design and Test Generation of C-testable High Speed Dividers," IEE Proceedings, Computers and Digital Techniques,.Vol.142, No.3, pp.193-200, May 1995.
  36. J.-W. Kang, C.L. Wey, and P.D. Fisher, "Applications of Bipartite Graphs for Race-free State Assignment," IEEE Trans. on Computers, Vol.44, No.8, pp. 1002-1011, August 1995.
  37. C.L. Wey, S. Krishnan, and S. Sahli, "Test Generation and Concurrent Error Detection in Current-Mode A/D Converters," IEEE Trans. on CAD, Vol. 14, No.10, pp. 1191-1198, October 1995.
  38. R. Huang and C.L. Wey, "Simple Low-Voltage, High-speed, High-Linearity V-I Converter with S/H for Analog Signal Processing Application," IEEE Trans. on Circuits and Systems. Part II. Analog and Digital Signal Processing. Vol.43, No.1, pp.52-55, January 1996.
  39. C.L. Wey, "Built-In Self-Test (BIST) Design of High-Speed Carry-free Dividers," IEEE Trans. on VLSI Systems, Vol. 4, No. 1, pp. 141-145, March 1996.
  40. R. Huang and C.L. Wey, "Design of High-speed, High-accuracy Current Copiers for Low-Voltage Analog Signal Processing Applications," IEEE Trans. on Circuits and Systems, Part II. Analog and Digital Signal Processing. Vol.43, No.12, pp.836-839, December 1996
  41. C.L. Wey, "Built-in Self-Test (BIST) Design of Current-mode Algorithmic A/D Converter" IEEE Trans. on Instrumentation and Measurement. Vol. 46, No. 3, pp. 667-671, June 1997.
  42. T.-H. Pan and C.L. Wey, "GRASS: an Efficient Gate re-assignment Algorithm for Inverter Minimization in Post Technology Mapping," IEE Proceedings, Computers and Digital Techniques, vol. 144, No. 5, pp.348-352, September 1997.
  43. C.-P. Wang and C.L. Wey, "Fault Macromodel for Switches in Switched-Current Circuits," International Journal of Circuit Theory and Application, Vol. 26, pp.93-102, January 1998.
  44. R. Huang and C.L. Wey, "A High-performance CMOS Oversampling Current Sample/Hold (S/H) Circuit Using Feedforward Approach." IEEE Trans. on Circuits and Systems, Part II. Analog and Digital Signal Processing, No. 47, No. 3, pp. 395-399, March 1998.
  45. W.-H. Huang and C.L. Wey, "ATPRG: An Automatic Test Program Generator Using HDL-A for Fault Diagnosis of Analog/Mixed-Signal Integrated Circuits," IEEE Trans. on Instrumentation and Measurement, Vol.47, No.2, pp.426-431, April 1998.
  46. C.L. Wey and M.-D. Shieh, "Design of High-Speed Square Generator," IEEE Trans. on Computers, Vol. 47, No. 9, pp.1021-1026, September 1998.
  47. W.-H. Huang and C.L. Wey, "Diagnosability Analysis of Analog Circuits," International Journal of Circuit Theory and Application. Vol.26, No.5, pp.439-451, September 1998.
  48. J.-S. Wang and C.L. Wey, "A 12-bit, 100ns/b, 1.9mW CMOS Switched-Current Cyclic A/D Converter," IEEE Trans. on Circuits and Systems, Part II. Analog and Digital Signal Processing. Vol.46, No.5, pp.507-516, May 1999.
  49. J.-S. Wang and C.L. Wey, "Design and Analysis of High Performance Current Reference Generators for Low-Power CMOS Data Converters," IEEE Trans. on Circuits and Systems, Part II. Analog and Digital Signal Processing. Vol.46, No.5, pp.647-652, May 1999.
  50. Y. Wan and C.L. Wey, "Efficient Algorithms for Binary Logarithmic Conversion and Addition," IEE Proceedings, Computers and Digital Techniques, Vol.146, No.3, pp.168-176, May 1999.
  51. C.L. Wey and C.-P. Wang, "A Fast Radix-4 SRT Divider and Its VLSI Implementation," IEE Proceedings, Computers and Digital Techniques, Vol. 146, No.4, pp.205-210, July 1999.
  52. C.L. Wey and W.-H. Huang, "Redesignability Check of Analog Circuits with Incomplete Implementation Information," IEEE Trans. on Circuits and Systems, Part I: Fundamental Theory and Applications, Vol. 46, No.8, pp.939-949, August 1999.
  53. Y. Wan, M.A. Khalil, and C.L. Wey, "Efficient Conversion Algorithms for Long-Word-Length Binary Logarithmic Numbers and Hardware Implementation," IEE Proceedings, Computers and Digital Techniques. Vol. 146, No.6, pp.295-301, November 1999.
  54. R. Huang, J.-S. Wang, and C.L. Wey, "A Fully Differential Current Copier for Performance Improvement," International Journal of Circuit Theory and Applications. Vol. 28, No.2, pp.  101-108, March 2000.
  55. C.-P. Wang and C.L. Wey, "Design of High performance Current Comparator as Built-In Testers of CMOS Switched-Current Circuits," International Journal of Analog Integrated Circuits and Signal Processing, Vol.23, No.3, pp.179-188, June 2000.
  56. C.L. Wey, "Design of Fast High-Radix SRT Dividers and Their VLSI Implementation," IEE Proceedings, Computers and Digital Techniques, Vol.147, No.4, pp.275-282, July 2000.
  • C.-P Wang, A.A. Hatzopoulos, and C.L. Wey, "A Built-in Self-test (BIST) Scheme for Analog Circuits and Systems," IEEE Trans. on Instrumentation and Measurement.
  • W.-H. Huang and C.L. Wey, "Efficient Test Points Selection Algorithms for Easily Testable Analog Circuits," IEEE Trans. on Circuits and Systems, Part I, Fundamental Theory and Applications. (in review)
  • M.A. Khalil and C.L. Wey, "Redesignability Check of Digital Circuits with Incomplete Implementation Information," IEEE Trans.  on Circuits and Systems, Part I.  Fundamental Theory and Applications. (in review)
  • J.-S. Wang and C.L. Wey, "A 11-b, 100MS/s, 4.4mW CMS Switched-Current Digital-to-Analog Converter," IEEE Trans. on Circuits and Systems, Part II. Analog and Digital Signal Processing. (in review)
  • C.-P. Wang and C.L. Wey, " Efficient Testability Design Methodologies for Analog/mixed-Signal Integrated Circuits," International Journal of Circuit Theory and Application. (in review)

    •  

    B. Book Chapters

    1. C.L. Wey, C.-c. Wu, and R. Saeks, "Analog Fault Diagnosis," Testing and Diagnosis of VLSI and ULSI, Ed. by M. Sami and F. Lombardi, Kluwer Academic Publisher, pp.117-150, 1988.
    2. F. Lombardi and C.L. Wey, "On Front Reconfiguration of VLSI Arrays," Testing and Diagnosis of VLSI and ULSI, Ed. by M. Sami and F. Lombardi, Kluwer Academic Publisher, pp.429-468, 1988.
    3. C.L. Wey and R. Saeks, "On the Implementation of Analog ATPG: The Linear Case," Analog Fault Diagnosis, Edited by R.W. Liu, IEEE PRESS, 1989.
    4. C.L. Wey, "A Searching Approach Self-Testing Algorithm for Analog Fault Diagnosis," Testing and Diagnosis of Analog Circuits and Systems, Edited by R.W. Liu, Van Nostrand Reinhold, New York,, pp.147-185, 1991.
    5. C.L. Wey, "Design and Test of CMOS Switched-Current Circuits," Analog and Mixed-Signal Test, Edited by B. Vinnakota, Prentice-Hall, Inc., 1998.

    C. Conference Papers

    1. C.-c. Wu, K. Nakajima, C.L. Wey, and R. Saeks, "Analog fault diagnosis with failure bounds," Proc. 24th Midwest Symp. on Circuits and Systems, Albuquerque, NM, pp.515-520, June 1981.
    2. C.L. Wey, D. Holder, and R. Saeks, "On the Implementation of an Analog ATPG," Proc. IEEE 3rd Automatic Test Program Generation (ATPG) workshop, pp.33-36, San Francisco, CA, March, 1983.
    3. C.L. Wey, D. Holder, and R. Saeks, "On the Implementation of an Analog ATPG," Proc. IEEE international Symp. on Circuits and Systems. Newport Beach, CA, pp.1102-1105, May 1983.
    4. C.L. Wey and R. Saeks, "On the Implementation of Analog ATPG II," IEEE 4th Automatic Test Program Generation (ATPG) workshop, Washington D.C., February 1984.
    5. C.L. Wey and R. Saeks, "On the Implementation of an Analog ATPG: The Nonlinear Case," Proc. IEEE International Symp. on Circuits and Systems, Montreal, Canada, pp.213-216, May 1984.
    6. C.L. Wey, "Parallel Processing for Analog Fault Diagnosis," Proc. 27th Midwest Symp. on Circuits and Systems, Morgantown, WV, pp.435-438, June 1984.
    7. C.L. Wey, "UUT Modeling for Digital Test - A Self-Test Approach," Proc. IEEE Fourth Annual Phoenix Conference on Computers and Communications, Phoenix, AZ, pp.312-316, March 1985.
    8. C.L. Wey, "Design of Testability for Analog Fault Diagnosis," Proc. IEEE International Symp. on Circuits and Systems, Kyoto, Japan, pp.515-518, June 1985.
    9. F. Lombardi and C.L. Wey, "Fault Identification Algorithm for VLSI Systems," Proc. ICCD, International Conference on Computer Design: VLSI in Computers, Port Chester, NY, pp. 693-696, October 1985.
    10. F. Lombardi and C.L. Wey, "On a Multiprocessor System with Dynamic Redundancy," Proc. Real-Time Systems Symposium, San Diego, CA. pp. 3-12, December 1985.
    11. F. Lombardi and C.L. Wey, "Diagnosis and Fault Identification Algorithms for Large Scale Computing Systems," Proc. First International Conference on Supercomputing Systems, Tarpon Spring, FL, pp. 404-413. December 1985.
    12. C.L. Wey and F. Lombardi, "On a New Decision Process for t-diagnosis of an Analog System," Proc. IEEE International Symp. on Circuits and Systems, San Jose, CA, pp.1255-1256, May 1986.
    13. B.-L. Jiang, and C.L. Wey, "Multiple Fault Diagnosis with Failure Bound for Analog Circuits," Proc. IEEE International Symp. on Circuits and Systems, San Jose, CA, pp.1261-1264, May 1986.
    14. C.L. Wey, and F. Lombardi, "On the Repair of Programmable Logic Arrays," Proc. IEEE International Symp. on Circuits and Systems, San Jose, CA, pp.649-652, May 1986.
    15. C.L. Wey, T.Y. Chang, and M.K. Vai, "On the Design of Fault-Tolerant Programmable Logic Arrays," Proc. International Computer Symp., Tainan, Taiwan, pp.398-404, December 1986.
    16. C.L. Wey, "An Efficient Unrepairability Detection Scheme for Redundant RAM Test System," Proc. International Computer Symp., Tainan, Taiwan, pp.406-413, December 1986.
    17. C.L. Wey and F. Lombardi, "Efficient, Yet Simple Algorithms for Repairing Redundant RAMs," Proc. IEEE International Symp. on Circuits and Systems, Philadelphia, PA, pp. 871-874, May 1987.
    18. C.L. Wey and F. Lombardi, "Analysis and Design of Repairable PLAs," Proc. CompEuro, pp.363-366, May 1987.
    19. C.L. Wey, "On Yield Considerations for the Design of Redundant Programmable Logic Arrays," Proc. ACM/IEEE Design Automation Conference (DAC), pp.622-628, June 1987.
    20. B.-L. Jiang, and C.L. Wey, "Fault Prediction Process for Large Analog Circuit Networks," Proc. 30th Midwest Symp. on Circuits and Systems, pp. 132-135, August 1987.
    21. C.L. Wey, T.Y. Chang, and Y.F. Chen, "The Design of VLSI-Based Parallel Multipliers," Proc. 30th Midwest Symp. on Circuits and Systems, pp.97-104, August 1987.
    22. S.-M. Chang and C.L. Wey, "Test Generation for C-testable Array Multipliers," Proc. 25th Allerton Conference, Univ. of Illinois. pp. 1040-1049, Sept. 1987
    23. C.L. Wey, and T.Y. Chang, "Minimization of PLAs with Ground True Outputs," Proc. of 25th ACM/IEEE Design Automation Conference (DAC), Anaheim, CA. pp.421-426, June 1988.
    24. Chang, T.Y. and C.L. Wey, "Design and Test of Electrically Field-Repairable APLAs," Proc. 31st Midwest Symp. on Circuits and Systems, St. Louis, MO, pp.36-39, August 1988.
    25. C.L. Wey, and T.Y. Chang, "An Efficient Boolean Comparison Process for Logic Verification," Proc. 31st Midwest Symp. on Circuits and Systems, St. Louis, MO, pp.1175-1178, August 1988.
    26. C.L. Wey, Jiang, B.L., and G. Wierzba, "Built-In Self-Test for Analog Circuit Networks," Proc. 31st Midwest Symp. on Circuits and Systems, St. Louis, MO, pp.862-865, August 1988.
    27. C.L. Wey and S.M. Chang, "Built-In Self-Test (BIST) Design of C-Testable Baugh-Wooley Array Multiplier," Proc. 31st Midwest Symp. on Circuits and Systems. St. Louis, MO. pp.1186-1189, August 1988.
    28. C.L. Wey and S.M. Chang, "Test Generation of C-testable Array Dividers," Proc. IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD '88), Port Chester, NY, pp.140-144, October 1988.
    29. C.L. Wey and B.L. Jiang, "Built-In Self-Test (BIST) Design of Large Scale Analog Circuit Networks," Proc. 1989 IEEE International Symp. on Circuits and Systems, Portland, OR, pp.2048-2051, May 1989.
    30. C.L. Wey, S.-M. Chang, and J.Y. Jou, "An Efficient Output Phase Assignment for MultiLevel Logic Minimization," Proc. 1989 International Workshop on Logic Synthesis, North Carolina, May 1989.
    31. C.L. Wey, "Fault Location in Repairable Programmable Logic Arrays," Proc. IEEE International Test Conference (ITC), Washington, D.C. pp.679-685, August 1989.
    32. C.L. Wey S.-M. Chang, and J.Y. Jou, "OPAM: An Efficient Output Phase Assignment for Multilevel Logic Minimization," Proc. IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD '89), Cambridge, MA, pp.270-273. October 1989.
    33. C.L. Wey, "Output Phase Assignment for Logic Minimization," (invited), 2nd Workshop on CAD for VLSI, Taiwan, March, 1990.
    34. C.L. Wey, J. Ding, and T.Y. Chang, "Design of Repairable and Fully Diagnosable Folded PLAs for Yield Enhancement," Proc. 27th ACM/IEEE Design Automation Conf. (DAC), Orlando, FL, pp.327-332, June 1990.
    35. C.L. Wey, and J. Ding, "Design of Repairable and Fully Testable Folded PLAs for Yield Enhancement," Proc. IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD '90), Cambridge, MA, pp.112-115, September 1990.
    36. C.L. Wey and T.Y. Chang, "On the Design of Concurrent Error Detectable Multiply and Divide Arrays," Proc. International Computer Symposium, Hsinchu, Taiwan, ROC, pp.564-570, December 1990.
    37. C.L. Wey, "Concurrent Error Detection in Array Dividers by Alternating Input Data," Proc. IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD '91), Cambridge, MA, pp.114-117, October 1991.
    38. C.L. Wey, M.-D. Shieh, and P.D. Fisher, "On Synthesis for Testability of Asynchronous Sequential Logic Circuits," IFIP International Workshop on the Relationship between Synthesis, Test, and Verification. Berkeley, CA, November 1991.
    39. C.S. Lai and C.L. Wey, "An efficient Algorithm for Reducing Hardware Overhead in Self-Checking Circuits and Systems," Proc. 35th Midwest Symp. on Circuits and Systems, Washington, D.C., pp.1538-1541, August 1992.
    40. J.W. Kang, C.L. Wey, and P.D. Fisher, "An Efficient Modeling and Synthesis Procedure of Asynchronous Sequential Logic Circuits," Proc. 35th Midwest Symp. on Circuits and Systems, Washington, D.C., pp.512-515, August 1992.
    41. M.-D. Shieh, C.L. Wey, and P.D. Fisher, "Model of Asynchronous Finite State Machines and Their Pipelined Structures," Proc. 35th Midwest Symp. on Circuits and Systems, Washington, D.C., pp.659-662, August 1992.
    42. S. Krishnan, S. Sahli, and C.L. Wey, "Test Generation and Concurrent Error Detection in Current-Mode A/D converters," Proc. IEEE International Test Conference (ITC), Baltimore, MD., pp. 312-320, September 1992.
    43. S. Sahli, S. Krishnan, and C.L. Wey, "Design of Concurrent Error Detectable Current-Mode A/D converters," Proc. International Conference on Microelectronics, Tunisia, pp.1.1.1.1-4, December 1992.
    44. J.-W. Kang, C.L. Wey, and P.D. Fisher, "Race-free State Assignments Using Bipartite Graphs," Proc. of IEEE Symposium on Circuits and Systems, Chicago, pp.2560-2563. May 1993.
    45. M.-D. Shieh, C.L. Wey, and P.D. Fisher, "Scan Design for Asynchronous Sequential Logic Circuits Using SR-latches," Proc. 36th Midwest Symp. on Circuits and Systems, Detroit, August 1993.
    46. J.-W. Kang, C.L. Wey, and P.D. Fisher, "A Synthesis Procedure for Large-Scale Asynchronous Finite State Machines," Proc. 36th Midwest Symp. on Circuits and Systems, Detroit, August 1993.
    47. C.S. Lai and C.L. Wey, "Design of Fast, Yet Low Hardware Cost Self-Testing Berger Code Checkers," Proc. 36th Midwest Symp. on Circuits and Systems, Detroit, August 1993.
    48. C.L. Wey , M.-D. Shieh, and P.D. Fisher, "ASLCScan: A Scan Design Technique for Asynchronous Sequential Logic Circuits," Proc. IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD '93), Cambridge, MA, pp. 159-162, October 1993.
    49. R. Huang, and C.L., Wey, "A Simple Yet Accurate Current Copier," Proc. 37th Midwest Sympo. on Circuits and Systems, Lafayette, LA, pp. 121-124, August 1994.
    50. C.L. Wey, "Design of C-testable High Speed Dividers," Proc. 37th Midwest Sympo. on Circuits and Systems, Lafayette, LA, pp. 261-264, August 1994.
    51. S. Krishnan and C.L. Wey, "A Parallel Current-mode A/D Converter Array with a Common Current Reference-Generating Circuit," Proc. 37th Midwest Sympo. on Circuits and Systems, Lafayette, LA, pp.1168-1171, August 1994.
    52. C.L. Wey, "Concurrent Error Detection in High Speed Carry-free Dividers," Proc. IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD '94), Cambridge, Massachusetts, pp. 124-127, October 1994.
    53. R. Huang and C.L. Wey, "High-Speed, Low Voltage V-I Converters for Analog Signal Processing Appliactions," IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS' 94), Taipei, Taiwan, pp. 494-498, December 1994
    54. C.L. Wey, "Built-In Self-Test (BIST) Design of High-Speed Carry-free Dividers," Proc. IEEE Symposium on Circuits and Systems, Seattle, WA, pp.1916-1919, May 1995.
    55. C.L. Wey, A.Y. Tetelbaum, and T. Bickart, "A Performance-driven Placement Approach of Standard Cells," Proc. International Conference on Intelligent Systems, Gelengick, Russia, pp.31-35, September 1995.
    56. C.L. Wey, H. Wang, and C.-P. Wang, "A Self-timed Redundant-Binary to Binary Number Converter for Digital Arithmetic Processors," Proc. IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD '95), Austin, TX, pp. 386-389, October 1995.
    57. T.-H. Pan, H.-S. Kay, Y. Chun, and C.L. wey, "High-Radix SRT Division with Speculation of Quotient Digits," Proc. IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD '95), Austin, TX, pp.479-482, October 1995.
    58. R. Huang and C.L. Wey, "A High-Accuracy CMOS Oversampling Current Sample/Hold (S/H) Circuit Using Feedforward Approach," Proc. IEEE International Symposium on Circuits and Systems, Atlanta, GA, Vol. I, pp.65-68, May 1996.
    59. R. Huang and C.L. Wey, "A 5mW, 12-b, 50ns/b Switched-current Cyclic A/D Converter," Proc. IEEE International Symposium on Circuits and Systems, Atlanta, GA, Vol. I, pp.207-210, May 1996.
    60. C.-P. Wang, A.A. Hatzopoulos, and C.L. Wey, "A Test Paradigm for Analog and Mixed-signal Circuits and Systems," Proc. IEEE International Symposium on Circuits and Systems, Atlanta, GA, Vol. III, pp. 194-197, May 1996.
    61. C.-P. Wang and C.L. Wey, "Test Generation of Switched-current A/D converters," Proc. 2nd IEEE International Mixed Signal Testing Workshop, Quebec City, Canada, pp. 98-103, May 1996.
    62. R. Huang, C.-P. Wang, C. Grunewald, and C.L. Wey, "Design of high-accuracy CMOS oversampling current sample/hold (S/H) circuits," Proc. of 39th Midwest Symp. on Circuits and Systems, Iowa, pp.939-942, August 1996.
    63. C.L. Wey and C.-P. Wang, "VLSI Implementation of a fast radix-4 SRT division," Proc. of 39th Midwest Symp. on Circuits and Systems, Iowa, pp.65-68, August 1996.
    64. T.H. Pan and C.L. Wey, "An efficient gate re-assignment algorithm in post technology mapping," Proc. of 39th Midwest Symp. on Circuits and Systems, Iowa, pp.363-366, August 1996.
    65. C.L. Wey, "On Design of Efficient Square Generator," IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD '96), Austin, TX, pp. 506-513, October 1996.
    66. C.L. Wey, "Mixed-Signal Testing -- a Review," (invited) IEEE International Conference on Electronics, Circuits, and Systems, Rodos, Greece, pp.1064-1067, October 1996.
    67. C.-P. Wang and C.L. Wey, "Test Generation of Analog Switched-Current Circuits," Proc. Asian Test Symposiums, Taiwan, pp.376-381, November 1996.
    68. C.-P. Wang and C.L. Wey, "Efficient Testability Design Methodologies for Mixed-Signal/Analog Integrated Circuits," 3rd IEEE International Mixed Signal Testing Workshop, Seattle, WA, pp. 68-74, June 1997.
    69. W.-H. Huang and C.L. Wey, "Development of HDL-A Modeled Test Programs for Fault Diagnosis of Analog/Mixed-Signal Circuits," 3rd IEEE International Mixed Signal Testing Workshop, Seattle, WA, pp. 3-14, June 1997.
    70. R. Huang, J.-S. Wang, and C.L. Wey, "A Fully Differential Switched-Current ADC with Improved Performance," (invited) Proc. 40th Midwest Symp. on Circuits and Systems, Davis, CA, pp. 177-180, August 1997.
    71. C.L. Wey, "Development of Redesign Process for Digital VLSI Systems," Proc. 40th Midwest Symp. on Circuits and Systems, Davis, CA, pp. 1001-1004, August 1997.
    72. C.-P. Wang and C.L. Wey, "High-Accurate CMOS Current Comparator," Proc. 40th Midwest Symp. on Circuits and Systems, Davis, CA, pp. 346-349, August 1997.
    73. W.-H. Huang and C.L. Wey, "Development of Automatic Test System for Mixed-Signal/Analog Integrated Circuits," Proc. 40th Midwest Symp. on Circuits and Systems, Davis, CA, pp. 1434-1437, August 1997.
    74. C-.P. Wang, and C.L. Wey, "Development of Hierarchical Testability Design Methodologies for Mixed-Signal/Analog Integrated Circuits," IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD '97), Austin, TX, pp.468-473, October 1997.
    75. M. Jimenez, M. Shanblatt, and C.L. Wey, "Mapping Multiplication Algorithms into a Family of LUT-based FPGAs," 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays (FPGA'98), Monterey, CA, February 1998.
    76. M.A. Khalil and C.L. Wey, "Using Test Generation Techniques for Redesigning Digital VLSI Circuits with Incomplete Implementation Information," Proc. International Conference on Chip Technology, Hsinchu, Taiwan, April 1998.
    77. J.-S. Wang and C.L. Wey, "Accurate CMOS Switched-Current Divider Circuits," Proc. IEEE International Symposium on Circuits and Systems, Monterey, CA,  pp. 53-56 (Vol I),May 1998.
    78. J.-S. Wang and C.L. Wey, "A 12-bit, 100ns/b, 1.9mW CMOS Switched-Current Cyclic A/D Converter," Proc. IEEE International Symposium on Circuits and Systems, Monterey, CA, pp. 416-419 (Vol. VI), May 1998
    79. Y. Wan and C.L. Wey, "Efficient Algorithms for Binary Logarithmic Conversion and Addition," submitted to Proc. IEEE International Symposium on Circuits and Systems, Monterey, CA, pp. 233-236 (Vol. V), May 1998.
    80. C.L. Wey and M.A. Khalil, "Redesignability Analysis of Digital VLSI Circuits with Incomplete Implementation Information," Proc. IEEE International Symposium on Circuits and Systems, Monterey, CA, pp.147-150 (Vol. VI), May 1998.
    81. J.-S. Wang, W.-H. Huang, and C.L. Wey, "Built-In Tester for CMOS Switched-Current Circuits in Low-Power/Low-Voltage Mixed-Signal Integrated Circuits," Proc. 4th IEEE International Mixed-Signal Workshop, Hague, Netherlands, June 1998.
    82. J.-S. Wang, W.-H. Huang, and C.L. Wey, "Fault Simulation of Built-In Tester for CMOS Switched-Current Circuits," Proc. IEEE Midwest Symposium on Circuits and Systems, Notre Dame, Indiana, pp. 212-215, August 1998.
    83. J.-S. Wang and C.L. Wey, "A 10-b, 100MS/s, 2.8mW CMOS Switched-Current DAC for Low-Power/Low-Voltage Signal Processing Applications," Proc. IEEE Midwest Symposium on Circuits and Systems, Notre Dame, Indiana, pp.526-529, August 1998.
    84. J.-S. Wang, R. Huang, and C.L. Wey, "Synthesis of Optimal Current Copiers for Low-Power/Low-voltage Switched-Current Circuits," Proc. IEEE Midwest Symposium on Circuits and Systems, Notre Dame, Indiana, pp.220-223, August 1998.
    85. M.A. Khalil and C.L. Wey, "Redesign Strategies for Digital VLSI Circuits with Incomplete Implementation Information," Proc. IEEE Midwest Symposium on Circuits and Systems, Notre Dame, Indiana, pp.264-267, August 1998.
    86. W.-H. Huang, J.A. Resh and C.L. Wey, "On Synthesis of Manufacturable and Testable Analog Integrated Circuits," Proc. IEEE Midwest Symposium on Circuits and Systems, Notre Dame, Indiana, pp.340-343, August 1998.
    87. J.-S. Wang and C.L. Wey, "Design of High-Performance CMOS Switched-Current D/A Converters for Low-Power/Low-Voltage Signal Processing Applications," Proc. IEEE International Conference on Electronics, Circuits, and Systems, Lisboa, Portugal, pp.1.19-1.22, September 1998.
    88. C.L. Wey and W.-H. Huang, "Test Point Selection Process and Diagnosability Analysis for Analog Integrated Circuits," Proc. IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD '98), Austin, TX, pp.582-587, October 1998.
    89. C.L. Wey, D.M. Aslam, and B. Kim, "Development of Embedded Testers Using Nano-Probes for Mnaufacturability Enhancement of Microelectronic Circuits and Systems", presented in DAPRA Tri-Service MEMS Based INSs Workshop, Alabama, December 1998.
    90. J.-S. Wang and C.L. Wey, "A 11-b, 100MS/s, 4.4mW CMOS Switched-Current Digital-to-Analog Converter," Proc. IEEE Midwest Symposium on Circuits and Systems, Las Cruces, NM, August 1999.
    91. J.-S. Wang and C.L. Wey, "Built-in Testers for Analog/Mixed-Siganl Circuits with CMOS Switched-current Data Converters Techniques," Proc. IEEE E/IT Conference, Chicago, June 2000.
    92. M.A. Khalil and C.L. Wey, "REDCI3: Redesignability Check for Digital VLSI Circuits with Incomplete Implementation Information," Proc. IEEE Midwest Symposium on Circuits and Systems, E. Lansing, MI, August 2000.
    93. D.T. Rover, B. Cheng, C.L. Wey, and M. Mutka, "Incorporating Large-scale Projects into a Multi-Disciplinary Approach to Embedded Systems," Proc. International Conference on Engineering Education, Taipei, Taiwan, pp.105-108, August 2000.
    94. J.S. Wang and C.L. Wey,  "A Low-Voltage Low-Power 13b Pipelined Switched-current Cyclic A/D Converter" , Proc. the IEEE 2nd Dallas CAS Workshop on Low Power and Low Voltage Analog and Mixed Signal Circuits & Systems, Dallas, Texas, March, 2001.
    95. M.A.  Khalil and C.L. Wey, "High-Voltage Stress Test Paradigms of Analog CMOS ICs for Gate-Oxide Reliability Enhancement," Proc. IEEE VLSI Test Symposium, Marina del Rey, CA, 2001.
    96. M.A. Khalil and C.L. Wey, “Extreme-Voltage Stress Vector Generation of Analog CMOS ICs for Gate-Oxide Reliability Enhancement,” Proc. International Test Conference, Baltimore, MD, 2001.
    D. Short Courses
    1. "Design for Testability of Analog Circuits,"East Lansing, Michgian, June 1988, for the project 'Advanced Design Methodologies for Large-Scale Electronic Circuits," spnsored by National Science Foundation.
    2. "Fault-tolerant VLSI Array Structures," Workshop on Fault-tolerant Computing, Microelectronics and Information Center, National Chiao-Tung Univ., June 1989.
    3. "Tutorial on Synthesis for Testability", 2nd Workshop on CAD for VLSI, Taiwan, March 1990.
    4. "Tutorial on Logic Synthesis," Workshop on Synthesis and Testability, National Taiwan University, Taiwan, May 1990
    5. "Tutorial on Synthesis for Testability,"Workshop on Synthesis and Testability, National Taiwan University, Taiwan., May 1990.
    6. "Built-In Self-Test Design of Analog and Digital Circuits," 1990 Workshop on VLSI Testing, National Chiao-Tung University, Taiwan, August 1990.
    7. "Synthesis and Design of Asynchronous Sequential Circuits and Systems,"  Workshop on VLSI Synthesis, Taipei, Taiwan, July 1992
    8. "Analog IC Design and Synthesis," 1992 Workshop on VLSI Designs, Taipei, Taiwan, July 1992.
    9. "Design and Test of Current-Mode Signal Processing Circuits for Sensor Array Implementation," Microelectronics and Information Center, National Chiao-Tung University, November 1992.
    10. "Some Issues on Technology Mapping for Standard Cells in Logic Synthesis,"4th VLSI/CAD Workshop, Nantou, Taiwan. August 1993.
    11. "Technology for Integrated Circuit (IC) Design and Fabrication", E. Lansing, Michigan, February 1995. for Institute of International Education,  United Nations, under Short-term US-based training for USAID Regional Support Mission for East Asia (RSM/EA) and the National Science and Technology Department Agency (NSTDA) conducted by IIE through the Department of Technical and Economic Corporation (DTEC) in connection with the Science and Technology for Development Project (Project No. 493-0340)
    12. "Mixed-Signal Testing -- a Review," IEEE International Conference on Electronics, Circuits, and Systems, Rodos, Greece, October 1996.
    13. "Mixed-Signal Fault Models and Design-for-Test", IEEE Asian Test Symposium, Hsinchu, Taiwan, November 1996.
    14. "Design, Testing, and Fault Diagnosis of Analog/Mixed-Signal Integrated Circuits," Mixed-Signal Products, Semiconductor Group, Texas Instrument Inc., Dallas, Texas, July 1997.
    15. "Design and Test of Analog/Mixed-Signal Integrated Circuits," International Conference on Chip Technology, Hsinchu, Taiwan, April 1998.
    16. “Mixed-Signal IC Testing”, Niational Science Council, National Central University, Taiwan, Feb. 2000.
    17. "Mixed-Signal IC Design,” Semina Series (6 hours), Workshop on Mixed-signal IC Design, National Science Council/National Tamkang University,  July 2001.

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