Krishnan Sundaresan

E-mail: sundare2-at-egr-dot-msu-dot-edu
Web: http://www.msu.edu/~sundare2

RESEARCH INTERESTS

• Power and temperature-aware processor design, VLSI computer-aided design, Embedded systems and code compression.

EDUCATION

• Ph. D., Department of Electrical & Computer Engineering, GPA: 3.83/4.0
  Major: Electrical & Computer Engineering, Michigan State Univ., East Lansing, MI, USA.
  Advisor: Dr. Nihar Mahapatra, Associate Professor
  Dissertation: Activity-Driven Analysis and Design Optimization of On-Chip Interconnects
• Master of Science (M.S), Sep. 2002,
  Major: Electrical Engineering, The State Univ. of New York, Buffalo, Buffalo, NY, USA
  
• Bachelor of Technology (B. Tech), Apr. 1999,
  Major: Electrical & Electronics Engineering, University of Calicut, India

• Member of Technical Staff, Processor CAD Division, Sun Microsystems Inc., Santa Clara, CA, USA, 12/2006 - Present.
• Summer Intern, High performance computing group, IBM India Research Labs, New Delhi, India, 06/2005 - 08/2005
  • Worked on bottleneck analysis and performance optimization of the SIMD floating-point unit in the Blue Gene/L CPU.
• Research & Teaching Assistant, Dept. of ECE, Michigan State Univ., East Lansing, MI, USA, 08/2003 - 12/2006.
• Firmware Engineer, Product development labs, Thomson Consumer Electronics (India) Ltd., 04/1999 – 07/2000
  • Hands-on experience in embedded hardware/software co-design, real-time operating systems, and product specification and life cycle processes.

SYNOPSIS OF RESEARCH

• Power and Temperature-Aware Interconnect Analysis and Optimization. Developed a microarchitecture level thermal model to track heat flow and estimate activity-dependent temperature rise in high-performance buses. Also developed a model to estimate delay impact of this temperature rise. Developed encoding techniques to simultaneously optimize bus energy and average/maximum wire temperature using these models. Papers describing this work have been published in major conferences (HPCA-2005, VLSID'05, DATE'06) and submitted to refereed journals (ACM-TACO, IEEE-TVLSI). The paper on thermal modeling for buses was nominated for a Best Paper award at HPCA.

• Power- and Cost-Efficient Dynamic Compression Techniques. Proposed various low-overhead dynamic compression schemes to simultaneously reduce bus power and cost. This work has been published in several leading conferences (ICCD'03 and '04, GLSVLSI'06).

• Information Pattern Aware Design. Conducted a most comprehensive study on the potential of compression in various storage and interconnection components of a microprocessor memory system. Co-authored papers that was published in various conferences (ASIC/SOC'02, IPCCC'03) and a refereed journal (JILP).

SKILLS

C, C++, SystemC, Perl, Verilog, MPI, Assembly language (MIPS, x86, SPARC), Unix/Linux, Solaris, VLSI-CAD (Cadence Virtuoso, Spectre, Verilog-XL, OCEAN scripting), SPICE, Real-time OS (RTX51, pSoS, Neutrino/QNX), IAR Embedded Workbench, ST9+ Toolkit, Code Composer Studio, Matlab, Visual Basic, LabVIEW, PVCS, SimpleScalar, SHADE, ILOG CPLEX and CONCERT.

COURSEWORK

Embedded architectures, Low power mixed-signal VLSI design, Advanced computer architecture, Advanced VLSI design, Analog circuits, Microelectronic device fabrication, Advanced switching theory, Parallel architecture, Computer communications, Algorithms analysis and design, Digital signal processing, Optical communications, Communication electronics

PROJECT EXPERIENCE

• Computer architecture
  • Advanced processor pipeline and memory sytem simulation using SimpleScalar,  SHADE, Simics, etc.
  • Performance analysis and optimization of high-performance systems
  • Integration of a SystemC-based bus model in SimpleScalar, Embedded architectures course, Spring 2005.
  • Investigation of performance impact of value-prediction based branch prediction, Advanced computer architecture course, Fall 2003.
• Digital/analog/mixed-signal VLSI design
  • High-speed bi-directional current mode signaling, Low power mixed-signal VLSI design course, Fall 2004.
  • 8-channel analog peak detector implementation with Cadence design tools in AMIC5N process, Summer 2003.
  • Lock-in amplifier design with a high-gain analog low noise amplifier (LNA) stage and a 1 Hz analog low pass filter.
  • Full custom implementation of low-power memory address bus encoder/decoder chip with Cadence design tools in 0.25u process
• Embedded system design
  • Picture-in-picture (PIP) hardware and embedded software for televisions [Client: Thomson Consumer Electronics, India, 1999-2000]
  • Advanced user interface modules (local language on-screen display, calendar) for televisions [Client: Thomson Consumer Electronics, India, 1999-2000]
  • PLC device driver for pSoS RTOS [Client: Pentasoft Technologies, India, 1999]
• Electronic instrumentation
  • Firmware for galvanometer scan controllers for prototype high-precision confocal microscope
  • Software in LabVIEW and interface in Visual Basic for operating a custom-deign confocal microscope
• DSP hardware/codecs
  • Narrow-band speech codec implementation on TMS320C6x hardware
  • G.729 CELP codec implementation for voice encoding in VoIP systems

PUBLICATIONS

• Please see List of publications

PROFESSIONAL MEMBERSHIPS AND SERVICES

• Member of IEEE and ACM.
• Member of ACM-SIGARCH and ACM-SIGDA
• Reviewer for 2005 IEEE Transactions on Computers and ACM/IEEE Design Automation Conference (DAC)
  
• Invited book reviewer for IEEE Circuits and Systems Magazine in 2003-04.
• Secondary reviewer for Intl. Conf. on Computer Design (ICCD), IEEE Intl. SoC Conference (SOCC), Intl. Conf. on VLSI Design, and Great Lakes Sym. on VLSI (GLSVLSI)

HONORS, AWARDS, AND ACHEIVEMENTS

• Nominated for best paper award at HPCA-11, 2005.
• MSU Graduate School Research Enhancement Award, Fall 2004.
  
• ACM-SIGARCH Fellowship to attend the 29th International Symposium on Computer Architecture (ISCA-29) in Anchorage, AK, May 2002
• Elected President of the Indian Graduate Student Association of SUNYB in 2001.