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Below is some selected projects I ever did in my past
research and classes.
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VLSI Design and Hardware:
Cadence tools:
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VLSI
implementation of a 16-bit data encryption algorithm which can be
applied to real-time 64-bit data encryption with a rate of about 270
Mb/s in a 0.35 
CMOS technology; |
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Design, layout,
and simulate a 3-bit flash ADC (0-5V) with minimum sampling rate of
4M Hz; |
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Design, layout,
and simulate a 16-bit (4x4) CMOS static RAM; |
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Design, layout,
and simulate a voltage-controlled ring oscillator. |
T-Spice tools:
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Design, layout, simulate, and
analyze an inverter; |
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Design, schematic, layout, and
simulate a 2-input NOR gate and a 4-input AND gate; |
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Design, schematic, layout, and
simulate 2-input CMOS and Pseudo-NMOS XNOR circuits; |
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As a main team member, design,
layout, simulate, fabricate, and test an Application Specific
Integrated Circuit (ASIC). Be responsible for designing a 3-bit
counter and a 4-to-1 multiplexer. This IC uses the MOSIS SCN3M_SUBM
( =0.3 ) process and the MOSIS 40-pin padframe for AMI’s
C5N fabrication process. |
VHDL and Verilog:
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Use the Aldec Active-HDL Entry and
Simulation tools to explicitly implement a carry look-ahead 2-bit
full adder; |
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Use the Block Diagram Editor of
Active-HDL 3.6 to hierarchically design and test with the testbench
files a 16-to-1 multiplexer; |
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Use the Xilinx Foundation Series ISE
3.1i tools to design and implement a binary MOD-4 up/down counter,
and download the VHDL code onto the Spartan-XL board to test its
functionality; |
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Design, schematic, simulate, and
test a 3-bit 4-functional ALU on the Xilinx Foundation Series; |
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Use StateCAD to design a state
diagram to control the taillights of an older-model Thunderbird car;
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Use the Xilinx tools to design a
microcomputer for 8-bit signed binary numbers with a 256 x 8 static
RAM memory; |
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Use the Cadence tools to properly
design and test the VHDL and Verilog modes for a JK flip-flop
circuit. |
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Systems Programming:
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Design a program that serves as a
limited replacement for “csh” shell in C; |
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Design a C++ program to simulate a
paged memory system with Clock algorithm; |
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Implement Shear sort algorithm with
multi-threading and semaphores in C on Solaris; |
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Implement Producer-Consumer problem
using WinNT threads, semaphores and mutexes. |
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TCP/IP and Network Programming:
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Implement File Transfer program in
Java using UDP on an unreliable channel with errors and packet loss
using CRCs and Stop & Wait protocol; |
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Implement a multi-threaded client
server application to do file processing. |
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