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Education :
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Michigan State University, East Lansing, MI (Aug 08 - present )
Master's of Science, Electrical and Computer Engineering
GPA : 3.92/4.0 -
Indian Institute of Technology-Kharagpur, India (Jul 04-May 08)
Bachelor's of Technology, Electrical Engineering
GPA : 8.12/10.0
Research Interests :
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Analog / Mixed Signal Circuit Design
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Learning in Sigma-Delta Modulators
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Noise Shaping Neural Networks
Research/Work Experience :
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Adaptive Integrated Microsystems Lab, Michigan State University
Graduate Research Assistant, Advisor : Dr. Shantanu Chakrabartty
1. M.S. Thesis : Presently working towards my master's thesis on "Resolution Enhancement in higher dimensional sigma-delta learners". The work focuses on finding lower dimensional manifolds in higher dimensional data space and exploiting this data correlation to achieve resolution enhancement using an adaptive ADC learning algorithm.
2. Also working on analog spectral feature extraction for a speaker verification system by using a Mel-frequency based band-pass filter bank. The complete system including a biquad filter tunable over the whole audible frequency range, the rectifier, the low pass filter and a first order sigma-delta ADC were designed and fabricated on a AMIS 0.5µm standard CMOS process. -
B.Tech Thesis : "Reduced order modeling of higher order systems" under the guidance of Prof. J Pal, Electrical Engineering, IIT Kharagpur.
The study involved reducing a linear, time-invariant higher order system to a lower order system keeping the system performance intact by using Genetic Algorithms. The same model order reduction was also achieved by Markov and time-moment parameter matching to ensure the stability of the system. -
Summer Internship : Signion Systems Pvt. Ltd.,Hyderabad, India.
"Optimization of Viterbi Algorithm used in SATCOM demodulator"
The project involved optimizing the viterbi code for both run time and memory so as to facilitate the upgradation of the demodulator from continuous mode to burst mode of operation. The optimization yielded 25% run time reduction in worst case scenario even under the severe compiler optimization limitations. -
Advanced VLSI Design Laboratory, IIT Kharagpur (May - June 2006)
"Design and implementation of a N-bit Wallace Tree multiplier". The time complexity of the multiplier was successfully reduced from O(n^2) to O(n*logn) by using fast adders instead of ripple carry adders.
Term Projects:
At MSU :
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Optimization of propagation delay, energy and area in an output-pin driver. (ECE-813 , Fall - 2008)
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Design of a charge pump based decorrelation system using sigma-delta learner. (ECE-832 , Spring - 2009)
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End-to-end deisgn of a basic Pulse Amplitude Mosulation (PAM) system. (ECE-865, Fall - 2009)
At IIT Kharagpur :
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Design of a control panel for a microwave oven working in different modes and power levels.
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Design of the triggering circuit for a buck converter.
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Study of an Proportional-Integrative-Differential (PID) controller on a process simulator and level control in a coupled tank.
Skills :
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Programming languages : C, C++, Verilog HDL, html
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Software : Cadence tools, Matlab/Simulink, PSPICE, AutoCAD, Mathematica, Code
Composer Studio, Protel DXP, LaTex
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Operating systems : Windows, Ubuntu
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Foreign Languages : French (basic skills)
Awards and Scholarships :
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Top 1% in India in the All India Joint Entrance Examination (JEE) for admission into the Indian Institute of Technology.
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State Rank - 27, Polytechnic Entrance Examination - 2002.
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State Rank - 3, Andhra Pradesh Regional Junior College Entrance Examination - 2002.
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MCM Scholarship, IIT Kharagpur - 2004 to 2008.
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Pratibha Scholarship, Govt. of Andhra Pradesh - 2004.
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Amongst the Top 100 selected from all over India in the Scholastic Aptitude Test (SAT) - 2002.