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S. Dutt and N.R. Mahapatra, "Parallel A* algorithms and their performance on hypercube multiprocessors," Proc. Seventh International Parallel Processing Symposium (IPPS 1993), pp. 797-803, Newport, CA, Apr. 13-16, 1993.
N.R. Mahapatra and S. Dutt, "Scalable duplicate pruning strategies for parallel A* graph search," Proc. Fifth IEEE Symposium on Parallel and Distributed Processing (SPDP 1993), pp. 290-297, Dallas, TX, Dec. 1-4, 1993.
N.R. Mahapatra and S. Dutt, "New anticipatory load balancing strategies for parallel A* algorithms," DIMACS Workshop on Parallel Processing of Discrete Optimization Problems, Rutgers University, NJ, Apr. 28-29, 1994 (Invited Paper).
S. Dutt and N.R. Mahapatra, "Scalable load balancing strategies for parallel A* algorithms," Journal of Parallel and Distributed Computing, special issue on Scalability of Parallel Algorithms and Architectures, Vol. 22, No. 3, pp. 488-505, Sep. 1994. pdf
S. Dutt and N.R. Mahapatra, "Node covering, error correcting codes and multiprocessors with very high average fault tolerance," Proc. 25th International Symposium on Fault-Tolerant Computing (FTCS-25), pp. 320-329, Pasadena, CA, Jun. 27-30, 1995.
N.R. Mahapatra and S. Dutt, "New anticipatory load balancing strategies for parallel A* algorithms," American Mathematical Society's DIMACS Series in Discrete Mathematics and Theoretical Computer Science---Parallel Processing of Discrete Optimization Problems, Vol. 22, pp. 197-232, 1995. pdf
N.R. Mahapatra and S. Dutt, "Sequential and parallel branch-and-bound search under limited-memory constraints," Proc. Parallel Optimization Colloquium (POC 1996), pp. 147-165, Versailles, France, Mar. 25-27, 1996 (Invited Paper).
N.R. Mahapatra and S. Dutt, "Random seeking: A general, efficient, and informed randomized scheme for dynamic load balancing," Proc. 10th International Parallel Processing Symposium (IPPS 1996), pp. 881-885, Honolulu, Hawaii, Apr. 15-19, 1996.
N.R. Mahapatra and S. Dutt, "Hardware-efficient and highly-reconfigurable 4- and 2-track fault-tolerant designs for mesh-connected arrays," Proc. 26th International Symposium on Fault-Tolerant Computing (FTCS-26), Sendai, Japan, pp. 272-281, Jun. 25-27, 1996.
N.R. Mahapatra and S. Dutt, "Scalable global and local hashing strategies for duplicate pruning in parallel A* graph search," IEEE Transactions on Parallel and Distributed Systems, Vol. 8, No. 7, pp. 738-756, Jul. 1997. pdf
S. Dutt and N.R. Mahapatra, "Node covering, error correcting codes and multiprocessors with very high average fault tolerance," IEEE Transactions on Computers, Vol. 46, No. 9, pp. 997-1015, Sep. 1997. pdf
N.R. Mahapatra and S. Dutt, "Adaptive Quality Equalizing: High-performance load balancing for parallel branch-and-bound across applications and computing systems," Proc. Joint 12th International Parallel Processing Symposium (IPPS 1998)/9th Symposium on Parallel and Distributed Processing Symposium (SPDP 1998), pp. 796-800, Orlando, FL, Mar. 30 - Apr. 3, 1998. pdf
N.R. Mahapatra and S. Dutt, "Efficient network-flow based techniques for dynamic fault reconfiguration in FPGAs," Proc. 29th Annual International Symposium on Fault-Tolerant Computing (FTCS-29), pp. 122-129, Madison, WI, Jun. 15-18, 1999. pdf
N.R. Mahapatra and S. Dutt, "Sequential and parallel branch-and-bound search under limited-memory constraints," The IMA Volumes in Mathematics and its Applications---Parallel Processing of Discrete Problems, P. Pardalos (ed.), Vol. 106, pp. 139-158, Springer-Verlag New York, Inc., 1999. pdf
N.R. Mahapatra and R. Janakiraman, "Gate triggering: A new framework for minimizing glitch power dissipation in static CMOS ICs and its ILP-based optimization," Proc. Third IEEE International Caracas Conference on Devices, Circuits and Systems (ICCDCS 2000), pp. C 109:1-7, Cancun, Mexico, Mar. 15-17, 2000. pdf
N.R. Mahapatra, S.V. Garimella, and A. Tareen, "An empirical and analytical comparison of delay elements and a new delay element design," Proc. IEEE Computer Society Annual Workshop on VLSI (WVLSI 2000), pp. 81-86, Orlando, FL, Apr. 27-28, 2000.
N.R. Mahapatra, S.V. Garimella, and A. Tareen, "Efficient techniques based on gate triggering for designing static CMOS ICs with very low glitch power dissipation," Proc. 2000 IEEE International Symposium on Circuits and Systems (ISCAS 2000), Vol. II, pp. 537-540, Geneva, Switzerland, May 28-31, 2000. pdf
N.R. Mahapatra and S. Dutt, "Random seeking: A general, efficient, and informed randomized scheme for dynamic load balancing," International Journal of Foundations of Computer Science, special issue on Randomized Computing, Vol. 11, No. 2, pp. 231-246, 2000. pdf
N.R. Mahapatra and S. Dutt, "Hardware-efficient and highly-reconfigurable 4- and 2-track fault-tolerant designs for mesh-connected arrays," Journal of Parallel and Distributed Computing, Vol. 61, No. 10, pp. 1391-1411, Oct. 2001. pdf
N.R. Mahapatra, J. Liu, K. Sundaresan, S. Dangeti, and B.V. Venkatrao, "An analysis of the potential of compression in improving memory system performance, power consumption, and cost," Proc. 2nd Annual Workshop on Memory Performance Issues (WMPI 2002), held in conjunction with 29th International Symposium on Computer Architecture (ISCA 2002), Anchorage, AK, May 25, 2002.
N.R. Mahapatra, J. Liu, K. Sundaresan, S. Dangeti, and B.V. Venkatrao, "The performance advantage of applying compression to the memory system," Proc. ACM SIGPLAN Workshop on Memory System Performance (MSP 2002), held in conjunction with ACM SIGPLAN 2002 Conference on Programming Language Design and Implementation (PLDI 2002), Berlin, GERMANY, Jun. 16, 2002.
N.R. Mahapatra, A. Tareen, and S.V. Garimella, "Comparison and analysis of delay elements," Proc. 45th IEEE Midwest Symposium on Circuits and Systems (MWSCAS 2002), Vol. 2, pp. 473-476, Tulsa, OK, Aug. 4-7, 2002. pdf
J. Liu, N.R. Mahapatra, K. Sundaresan, S. Dangeti, and B.V. Venkatrao, "Memory system compression and its benefits," Proc. 15th Annual IEEE International ASIC/SOC Conference (ASIC/SOC 2002), pp. 41-45, Rochester, NY, Sep. 25-28, 2002. pdf
S.K. Namilikonda, A.V. Sivalenka, and N.R. Mahapatra, "Scalable parallel branch-and-bound for protein structure prediction," Proc. 2003 SIAM Conference on Computational Science and Engineering (CSE 2003), San Diego, CA, Feb. 10-13, 2003.
A.V. Sivalenka and N.R. Mahapatra, "A comprehensive evaluation of parallel algorithms for the linear assignment problem," Proc. 2003 SIAM Conference on Computational Science and Engineering (CSE 2003), San Diego, CA, Feb. 10-13, 2003.
J. Liu, N.R. Mahapatra, and K. Sundaresan, "Hardware-only compression to reduce cost and improve utilization of address buses," Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), pp. 220-221, Tampa, FL, Feb. 20-21, 2003.
K. Sundaresan and N.R. Mahapatra, "Code compression techniques for embedded systems and their effectiveness," Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), pp. 262-263, Tampa, FL, Feb. 20-21, 2003.
N.R. Mahapatra, J. Liu, K. Sundaresan, S. Dangeti, and B.V. Venkatrao, "The potential of compression to improve memory system performance, power consumption, and cost," Proc. 22nd IEEE International Performance, Computing, and Communications Conference (IPCCC 2003), pp. 343-350, Phoenix, AZ, Apr. 9-11, 2003. pdf
K.R. Gandhi and N.R. Mahapatra, "A detailed study of hardware techniques that dynamically exploit frequent operands to reduce power consumption in integer function units," Proc. Second Annual Workshop on Duplicating, Deconstructing, and Debunking (WDDD 2003), held in conjunction with 30th International Symposium on Computer Architecture (ISCA 2003), pp. 76-84, San Diego, CA, Jun. 8, 2003.
K.R. Gandhi and N.R. Mahapatra, "A study of hardware techniques that dynamically exploit frequent operands to reduce power consumption in integer function units," Proc. 21st IEEE International Conference on Computer Design (ICCD 2003), pp. 426-428, San Jose, CA, Oct. 13-15, 2003.
N.R. Mahapatra, J. Liu, and K. Sundaresan, "Hardware-only compression of underutilized address buses: Design and performance, power, and cost analysis," Proc. 21st IEEE International Conference on Computer Design (ICCD 2003), pp. 234-239, San Jose, CA, Oct. 13-15, 2003.
N.R. Mahapatra and S. Dutt, "Adaptive Quality Equalizing: High-performance load balancing for parallel branch-and-bound across applications and computing systems," Parallel Computing, Vol. 30, No. 7, pp. 867-881, Jul. 2004.
S. Krishnamohan and N.R. Mahapatra, "An efficient error-masking technique for improving the soft-error robustness of static CMOS circuits," Proc. IEEE International SOC Conference (SOCC 2004), pp. 227-230, Santa Clara, CA, Sep. 12-15, 2004.
J. Liu, K. Sundaresan, and N.R. Mahapatra, "Dynamic address compression schemes: A performance, energy, and cost study," Proc. 22nd IEEE International Conference on Computer Design (ICCD 2004), pp. 458-463, San Jose, CA, Oct. 11-13, 2004.
S. Krishnamohan and N.R. Mahapatra, "A highly-efficient technique for reducing soft errors in static CMOS circuits," Proc. 22nd IEEE International Conference on Computer Design (ICCD 2004), pp. 126-131, San Jose, CA, Oct. 11-13, 2004.
K.R. Gandhi and N.R. Mahapatra, "Dynamically exploiting frequent operand values for energy efficiency in integer functional units," Proc. 18th International Conference on VLSI Design (VLSID 2005), pp. 570-575, Kolkata, India, Jan. 3-7, 2005.
J. Liu, K. Sundaresan, and N.R. Mahapatra, "Energy-efficient compressed address transmission," Proc. 18th International Conference on VLSI Design (VLSID 2005), pp. 592-597, Kolkata, India, Jan. 3-5, 2005.
K. Sundaresan and N.R. Mahapatra, "An accurate energy and thermal model for global signal buses," Proc. 18th International Conference on VLSI Design (VLSID 2005), pp. 685-690, Kolkata, India, Jan. 3-5, 2005.
K. Sundaresan and N.R. Mahapatra, "Accurate energy dissipation and thermal modeling for nanometer-scale buses," Proc. 11th International Symposium on High-Performance Architecture (HPCA 2005), pp. 51-60, San Francisco, CA, Feb. 12-16, 2005 (Nominated for Best Paper Award).
S. Krishnamohan and N.R. Mahapatra, "An analysis of the robustness of CMOS delay elements," Proc. 15th Great Lakes Symposium on VLSI (GLSVLSI 2005), pp. 412-415, Chicago, IL, Apr. 17-19, 2005.
S. Krishnamohan and N.R. Mahapatra, "Analysis and design of soft-error hardened latches," Proc. 15th Great Lakes Symposium on VLSI (GLSVLSI 2005), pp. 328-331, Chicago, IL, Apr. 17-19, 2005.
S. Krishnamohan and N.R. Mahapatra, "Increasing the energy efficiency of pipelined circuits via slack redistribution," Proc. 15th Great Lakes Symposium on VLSI (GLSVLSI 2005), pp. 436-441, Chicago, IL, Apr. 17-19, 2005.
S. Krishnamohan and N.R. Mahapatra, "Combining error masking and error detection plus recovery to combat soft errors in static CMOS circuits," Proc. 2005 International Conference on Dependable Systems and Networks (DSN 2005), pp. 40-49, Yokohama, Japan, Jun. 28 - Jul. 1, 2005.
N.R. Mahapatra, J. Liu, K. Sundaresan, S. Dangeti, and B.V. Venkatrao, "A limit study on the potential of compression for improving memory system performance, power consumption, and cost," The Journal of Instruction-Level Parallelism, Vol. 7, Jul. 2005 (http://www.jilp.org/vol7).
K. Sundaresan and N.R. Mahapatra, "Value-based bit ordering and clustering techniques for energy and thermal optimization of on-chip global signal buses," to appear in Proc. 9th Design, Automation and Test in Europe Conference (DATE 2006), Munich, Germany, Mar. 6-10, 2006.
K.R. Gandhi and N.R. Mahapatra, "Exploiting data-dependent slack using dynamic multi-VDD to minimize energy consumption in datapath circuits" to appear in Proc. 9th Design, Automation and Test in Europe Conference (DATE 2006), Munich, Germany, Mar. 6-10, 2006.
N.R. Mahapatra and S. Dutt, "An efficient delay-optimal distributed termination detection algorithm," accepted for publication in Journal of Parallel and Distributed Computing.
Contact information:  Phone: (517) 432-4617 • Fax: (517) 353-1980 • E-mail: nrm(@)egr.msu.edu
Last modified Thu Oct 20 18:20:34 EDT 2005