Operand Encoding and Operation Bypass for Microarchitecture Optimization
Modern microprocessors feature wide (64-bit) datapaths and are mostly designed with worst-case inputs in mind. However, such operands rarely occur; the most frequently occurring input operand words have strings or subwords (SWs) of 0's and 1's embedded in them. We are developing a general methodology to optimize microarchitectural modules for computation (e.g., functional units or FUs), communication (e.g., buses), and storage (e.g., pipeline registers, register files, caches, etc.) by exploiting such frequent operand SW values. It partitions operand words in a predetermined manner into SWs and encodes each SW value as either special (i.e., an all-0 or all-1 pattern) or regular (otherwise) using encoding bits. Hardware modules are similarly partitioned into submodules. A submodule's operation is bypassed when its input consists of an "exploitable" combination of SW values (e.g., combinations of special values or special and regular values). For example, communication or storage of just the encoding bits suffices for special values. Similarly, in FUs, output SWs of bypassed submodules are computed using an alternative, simpler, and lower-power means.
Copyright, Kaushal Gandhi, 2005