Quickstart Guide to Using
CADENCE AFFIRMA NCVHDL

Prepared by Sharad Kumar ,S00
(kumarsha@egr.msu.edu)
Reviewed by Arun Narayanan, F00
(arunkum2@egr.msu.edu)

---

Step 1 : Create the folder for the design.

          > mkdir  <folder_name>

Step 2 :  Setting up the environment.

To start using the Cadence tools one needs to source a script which contains all the necessary path and setup information to invoke the tool.  Type the following on the UNIX command prompt.

> source $SOFT/cadence

Create a user library called worklib in your design folder.
> mkdir  worklib

Two other setup files, listed below, are required before you can start using the tools. Copy the contents from here into your design folder. These files specify the path to libraries and also create a user work library. In this case the user work library has been called worklib but can be given any name.

1.  hdl.var

SOFTINCLUDE $CDS_INST_DIR/tools/inca/files/hdl.var
DEFINE USE_NEW_SIMWAVE_WINDOW ON
DEFINE EDITOR vi
DEFINE CDS_TEXT_EDITOR vi
DEFINE WORK worklib

2. cds.lib

SOFTINCLUDE $CDS_INST_DIR/tools/inca/files/cds.lib

-- This cds.lib file was made by the Notebook Startup
-- as part of a Create Work Area command
-- File Created at Tue Dec 21 3:32:44 1999
DEFINE worklib ./worklib
 
 

Step 3 :  Write VHDL code and testbench.
 
In this example we are  working with a design  file named trial.vhdthat has the following structure : (Note: Refer to any VHDL text for detail on VHDL constructs).
 
entity trial is
  port (
:
:
);
end trial;
 

architecture trial_rtl of trial is
begin

:
:
end trial_rtl;
The testbench for the design file, test_trial.vhd , has the following structure
 
entity test_trial is
end test_trial;

architecture tb_arch of test_trial is
component trial
           port (

:
:
                          );

begin

UUT : trial
           port map
                          (

:
:
                           );
 
:     -- Add your stimulus here
:
end tb_arch;
 
 
Step 4 :  Analyzing & elaborating the design.
 
On the Unix prompt all design files and testbench need to be analyzed and elaborated. The analyzer, ncvhdl, encapsulates two tools : the VHDL parser and the code generator. The parser performs syntactic and static semantic checking on the input source files. If no errors are found, compilation produces an internal representation for each HDL design unit in the source files. These intermediate objects are stored in a library directory [1].

The elaborator, ncelab, constructs a design hierarchy based on the instantiation and configuration information in the design, establishing signal connectivity, and computes initial values for all objects in the design. The elaborated design hierarchy is stored in a simulation snapshot file, which is used by the simulator.

Analyze the design.
> ncvhdl <filename.vhd>                           --(Generic Command)

(Note: Type ncvhdl -help for a complete list of available options)

For our specific case:

> ncvhdl trial.vhd
> ncvhdl test_trial.vhd

Elaborate the design.
>  ncelab my_lib.top:behav                      --(Generic Command)

( Note: my_lib is your library where design is kept, top is the name of the design entity and behav is the name of the design architecture. Type ncelab -help for a complete list of available options )

For our specific case

> ncelab worklib.trial:trial_rtl
> ncelab worklib.test_trial:tb_arch

(Note: The design file needs to be analyzed and elaborated before the testbench file.)
 
 

Step 5 :  Initiating the simulation.
 
At this stage the design has been successfully compiled (analyzed & elaborated). Now we would like to simulate the design to see whether it is functionally correct.

> ncsim my_lib.top                                 --(Generic Command)

For our specific case we would like to view the simulation in a GUI so also specify the -gui option)

> ncsim -gui test_trial &

(Note : We are simulating only the testbench. Our design was declared as a component in the testbench.)

You should see a simulator window as shown below.
 



Figure 1


Notice that the window in figure 1 displays the architecture of the testbench file. The menu's of this tool are quite extensive and provide the user with a lot of debugging facilities like setting breakpoints and watch values, which should sound familiar to users of C/C++ debugger. Another thing to note is that the lower portion of the window gives a command prompt (ncsim>). This allows you to type a command rather than choosing options from the menu. For large designs with many hierarchical .vhd files it is also possible to write scripts to do a complete design starting from compile to simulation.For our simple design we will, however, move on to the displaying the waveform for our design.
 
 

Step 6 :  Starting the DAI Signalscan.
 
Before invoking the Signalscan, it is important to select the signals as in figure 2 to display on the waveform. Choose
Select -> Signals   from the menu of the simulator (refer figure 1). Once the signal selection has been done your window should appear like figure 3.



Figure 2


To invoke the Signal scan click on the button   in the upper right corner (refer figure 1). You should see the DAI Signalscan with the signals you selected (figure 3).
 



Figure 3

Step 7 : Running the Simulation.

To start the simulation click on   in the simulator window. This will run the simulation to the end of the test vectors provided in the testbench file. There are run options to single step through the code  or step over  . Another nice way of running simulation is to specify the absolute or relative time of run. The following example runs the simulation for 500ns.
ncsim > run 500 ns
After having completed the simulation the DAI Signalscan displays the waveform of the individual signals (figure 4).
 



Figure 4

This concludes the brief tutorial for using AFFIRMA NCVHDL tools  in Cadence. The HELP on these tools is very good and extensive. Refer to this for any detailed description on using the advanced options for compiling, simulation and waveform viewing.

 
More information about the Cadence tools is available by either browsing through the HELP menu or by typing ob_ldv on the UNIX command prompt. This opens the Cadence OPENBOOK for the entire suite of tools available under the LDV 2.2 release.
 

References

[1]  Affirma NC VHDL Simulator Help.