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Current Research
Biomedical Microsystems
Microsystem Implementation
of Biosensor Arrays Based on Nanostructured Protein Interfaces
Chemiresistor
Instrumentation
On-Chip Temperature Controlled Array for Functional
Proteomics
On-Chip Readout of Electrochemical
Sensors: CMOS Potentiostats and Impedance Spectroscopy
Implantable Signal
Processing Circuitry for Neuroprosthetic Devices
Sensor Interface Circuits
Highly Adaptive Multi-Sensor
Readout and Communication Interface Circuits
AMSaC Mixed Signal Generic Test Board
Process-Scalable Optimization
of Wide-Issue Superscalar Microprocessors
Microsystem Implementation of  Biosensor
Arrays Based on Nanostructured Protein Interfaces
Description:
In a highly cross-disciplinary project, we have begun
developing chip-scale electrochemical systems for novel biointerfaces based
on soluble and membrane proteins.
These systems utilize uniquely fabricated on-chip electrode arrays [1] and
self assembled, nanostructured, tethered proteins [2] to realize new
technologies suitable for biosensors and protein characterization
instruments. This area of
research holds tremendous potential for truly groundbreaking developments
in highly sensitive, multianalyte sensors and powerful tools for analyzing
the function and response of newly expressed proteins.
While several international research groups are exploring protein-based interfaces,
we have been the first to report the integration of these technologies into
chip-scale platforms [3]. Our
recent work demonstrates techniques for fabricating electrochemical
biosensor arrays directly on the surface of integrated circuit chips [4],
paving the way for single-chip protein-array microinstruments.
Investigators:
Yue Huang.
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Chemiresistor
Instrumentation
 Description:
Chemiresistors (CR) made from gold-thiolate
mono-layer-protected nanoparticles (MPN) provide a powerful tranducer
element for sensing organic vapors. However, the CR usage is currently
limited by instrumentation. The CR
has a theoretical sensitivity well beyond what current circuitry is able to
measure. Also, the CR has a
capacitive response which would yield more information, but measurement of
this response is limited. The goal
of this research is to provide instrumentation capable of probing the CR to
its theoretical limits, and thus extending the possible applications of
this transducer.
Investigators:
Daniel Rairigh
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On-Chip Temperature Controlled
for Functional Proteomics
 Description:
In structural biology and
biotechnology, the characterization of the proteins encoded in some
genomes, such as Galdieria sulphuraria, without precise knowledge of
their functions, is a critical research obstacle today. One of important
factors of characterizing those membrane proteins is to keep appropriate
temperature to maintain their stability and activity. CMOS based on-chip micro systems can
offer better testing performance in terms of lower signal noise ratio, low
power consumption, and high through-output. This project focused on
developing an on-chip temperature controlled array microsystem platform
that includes integrated heaters, temperature sensors and CMOS temperature
control circuits, and thus providing a suitable multifunctional tool for
functional proteomics research.
Investigators:
Xiaowen Liu
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On-Chip
Readout of Electrochemical Sensors: CMOS Potentiostats and  Impedance Spectroscopy
Description:
In unison with the topic above, we have been
developing the backbone circuitry necessary to realize miniature
bioelectrochemical systems with on-chip measurement electronics. Utilizing state-of-the art mixed-signal
integrated circuit techniques, we developed a high performance potentiostat
that can resolve sub-picoampere currents, operate over six orders of magnitude
in base current, and perform on-chip cyclic voltammetry on a sensor array
[1,2]. This circuit is currently being tested
with electrochemical sensors for a journal paper to be submitted by Dec. 2006.
Electrochemical impedance spectroscopy (EIS) is another important
measurement technique for bio/chem-interfaces, but there are no existing
chip-scale EIS solutions. We have analyzed several EIS techniques
and evaluated their feasibility for on-chip implementation with biological
and chemical sensors [3]. We have created a new methodology and
circuit to rapidly perform EIS in the low frequency range [4] (invention
disclosure filed), as necessary for many biosensors.
With the proliferation of nano-technology sensors in recent years, we
anticipate these chip-scale readout circuits, particularly EIS, to be
critical for next generation sensory systems.
Investigators:
Chao Yang.
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Implantable Signal Processing
Circuitry for Neuroprosthetic Devices
Description:
Merging past achievements in digital signal
processors with our current and future focus on biomedical microsystems, we
have begun exploring the implementation of neural signal processing
hardware under the power and area constraints of implantable systems. We
have shown that multi-level discrete wavelet transform (DWT) can be
implemented on chip with low power and very limited area (~1mm2)
utilizing an integer lifting DWT scheme [1,2].
We have introduced a new circuit optimized for real-time DWT of
multi-channel neural signals [2] and shown that it is more efficient for
implantable applications than competing approaches [3-5]. Our
design of an area-power optimized integrated circuit for 32-channel,
5-level DWT in implantable neuroprosthetic applications will be described
in a submitted conference paper and a journal paper to be submitted by
early spring 2007.
Investigators:
Awais M. Kamboh
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AMSaC Mixed Signal Generic Test Board
 Description:
We have begun to
develop a generic test board to verify the functions and to evaluate the
performance of our chips. The goal of this project is to provide a platform
for a broad variety of digital, analog and mixed signal chips. This board
acts not only as an electrical interface between the device under test and
the PC, but it also offers specific functionalities using different types
of onboard ASICs. To achieve as much flexibility as possible, control
signals and test stimuli are provided by a reprogrammable FPGA. In order to
reduce the time and effort to access and process the data, a data
acquisition card is used.
Investigators:
Stefan Schorr
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Highly Adaptive Multi-Sensor
Readout and Communication Interface Circuits
Description:
As
a legacy of prior work integrating multi-parameter microsystems [1],
several generations of sensor interface circuits have been developed. Early versions [2-5] demonstrated adaptability
to different capacitive transducers.
We then introduced a new sensor bus structure uniquely tailored to
integrated microsystems with multiple intra-module sensor nodes [6]. Utilizing this sensor bus, subsequently
developed interface circuits provided a very high level of readout
configurability and system flexibility [7-9].
Our universal microsensor interface (UMSI) chip [10] achieved unprecedented
adaptability to many different sensor types and implemented numerous
performance enhancing features, such as online recalibration and
mixed-signal actuator control, not available in any other miniature,
low-power, sensor interface circuit.
We have also recently incorporated these ideas into a new system-on-chip
(SoC) implementation with an embedded controller and a highly hardware-efficient
sensor readout block [11]. This
chip has won two prizes in an SoC design contest sponsored by the
Semiconductor Research Corporation, and [11] is a finalist for Best Student
Paper in the upcoming IEEE Sensors Conference.
Investigators:
Chao Yang, Jichun Zhang, Junwei Zhou
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 Process-Scalable Optimization
of Wide-Issue Superscalar Microprocessors
Description: Combining an
understanding of circuit-level performance constraints with
architectural-level high throughput structures, we have analyzed the design
tradeoffs for wide-issue superscalar microprocessors as CMOS feature size
shrinks in the submicron regime. We have identified several effective
methods for decreasing delays in the processor instruction queue [1] and
designed circuits to significantly reduce processor delays with negligible
performance loss [2,3]. We have
shown that our hardware banking/segmenting approach can be adapted to match
performance characteristics of different wide-issue processors, enabling
significant performance improvement for both single program and
multi-program workloads [3,4].
Investigators:Chao Yang, Jichun Zhang, Junwei Zhou
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